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The supply chains of semiconductors and integrated devices supports industry across all economic sectors. Globally, the supply chain is experiencing a variety of stressors and disruptions, with effects that cascade across the economy, causing product delays and enterprise losses. However, quantitative models that support an understanding of how stressors influence supply chain performance are needed. Here we show how stress testing can be used for assessing the impact of disruptions on supply chain performance metrics and for characterizing system resilience. We demonstrate a framework that utilizes discrete event simulation for stress testing the resilience of a semiconductor supply chain. Our results include a comparison of resilience curves with and without risk management countermeasures, showing the resilience-enhancing benefits of various supply chain management strategies such as maintaining safety stock and sourcing from multiple suppliers. Supply chain managers can utilize stress testing principles and methodologies to configure their supply chain and engage in practices that contribute to system resilience. 

Reverse engineering (RE) is a widespread practice within engineering, and it is particularly relevant for discovering maliciousfunctionality in digital hardware components. In this paper, we discuss bitstream or firmware RE for field programable gate arrays (FPGAs). A bitstream establishes the configuration of the FPGA device fabric. Complete knowledge of both the physical device fabric and a specific bitstream should be sufficient to determine the complete configuration of the programmed FPGA. However, a significant challenge to bitstream RE arises because information about the FPGA fabric and interpretation of the bitstream is typically incomplete. The uncertainties limit the confidence in the correctness of any configuration determined through the RE process. This paper identifies representative sources of uncertainty in bitstream RE of FPGA devices.